Kaushik Vada.

Static timing, power, and the path from RTL to GDS.

Physical Design Intern Tenstorrent EE @ UC Riverside

By the numbers.

Every figure keeps its context — what was measured, against what, and where.

Experience

Three roles, newest first

Current role. September 2026 – Present Santa Clara, CA

Tenstorrent

Physical Design Intern

Timing the links between dies in a next-generation AI accelerator.

  • Static timing analysis on die-to-die interconnects in a next-generation AI accelerator SoC with RISC-V cores, using Synopsys PrimeTime with post-route netlists, SPEF parasitics, UPF power intent, and SDC constraints.
  • Multi-voltage timing paths through level shifters, connecting a dynamic-voltage SoC domain to a fixed-voltage PHY domain, evaluating voltage-dependent timing behavior.
  • Corner-specific parasitic extraction with Synopsys StarRC on Fusion Compiler databases, and automated RTL-to-GDS flows configured from synthesis through route optimization.
  • AI/ML-based corner selection, under investigation, targeting a reduction from approximately 46 PVT corners to 10, evaluating derating and guard-banding strategies to preserve timing coverage and reduce signoff turnaround.

June 2026 – September 2026 San Diego, CA

Arm

SoC Physical Design Intern

Floorplan to post-route: a tape-out candidate for an active SoC block.

  • Delivered a tape-out candidate for an active ARM AGI-CPU SoC block, incorporating activity-driven power optimization and two-pass placement optimizations, executing the Cadence Innovus flow from floorplanning through placement, CTS, routing, and post-route optimization. The implementation was advanced for downstream STA and timing evaluation.
  • Activity-driven power optimization, for 18.4–19.5% lower reported power versus baselines under matched workloads, after comparing multiple FSDB activity profiles to guide selection based on power and timing.
  • Co-developed a two-pass placement flow with Cadence engineers, reducing estimated power by 5.86% and cell area by 2.45%.
  • Codex-assisted statistical modeling of prior runs to guide setup-margin tuning, for 38.5% lower measured mean RX data-path delay, deliberately tightening constraints on positive-slack I/O paths to trigger optimization toward full-chip timing requirements.
  • Reusable STA and PrimeTime PX workflows, with analysis scripts to compare implementation results, audit generated Tcl/YAML against applied constraints, and support international engineering teams.

September 2025 – April 2026 Riverside, CA

VSCLab

Undergraduate Researcher · VLSI Systems & Computer Architecture Lab, University of California, Riverside

Pipeline stages and verification for a custom open-source RISC-V core.

  • Designing and implementing a custom open-source RISC-V CPU core, developing pipeline stages and verification infrastructure targeting full functional correctness.
  • Verilog and Synopsys RTL-to-gate flows applied in an active research environment, reinforcing skills in synthesis and gate-level simulation.
  • SDC timing constraints, authored and refined in Synopsys Design Compiler as part of the lab’s constraint-driven synthesis workflow.

Project · March 2026 – Present

MiniGPU-2

A custom graphics accelerator ASIC, from vertex transformation to rasterization.

  • Floorplanning and place-and-route in Cadence Innovus on a SAED 32nm checkpoint, iterating on timing and congestion for a custom ASIC.
  • RTL-to-gate synthesis, with a team, in Synopsys Design Compiler and Cadence Genus for a SystemVerilog graphics pipeline spanning vertex transformation and rasterization.
  • Dual-clock asynchronous FIFOs with Gray-coded pointer synchronizers to support communication across clock domains.

Skills

The toolkit.

Languages

  • Verilog
  • C/C++
  • Python
  • TCL

Tools

Synopsys

  • PrimeTime
  • PrimeTime PX
  • Design Compiler
  • Fusion Compiler
  • VCS

Cadence

  • Innovus

Xilinx

  • Vivado

Concepts

  • Physical Design
  • Floorplanning
  • Placement & Routing
  • Clock Tree Synthesis (CTS)
  • Static Timing Analysis (STA)
  • SDC Timing Constraints
  • Power Analysis & Optimization
  • RTL Design
  • Computer Architecture

Protocols

  • UART
  • APB
  • Valid/Ready Handshake

Education

University of California, Riverside

Bachelor of Science in Electrical Engineering

August 2023 – June 2027 Riverside, CA

GPA

3.93/4.00

University of California Regents Distinguished Scholar

Relevant coursework

  • Introduction to VLSI
  • Data Structures and Algorithms
  • Design and Architecture of Computer Systems
  • Machine Organization and Assembly Language
  • Digital Logic Design
  • GPU Architecture and Programming

Let’s talk.

Email is the fastest way to reach me.

kaushikvada3@gmail.com