Kaushik Vada
B.S. Electrical Engineering, University of California, Riverside
VLSI-focused electrical engineering student with hands-on experience in Verilog RTL design, FPGA development in Xilinx Vivado, and introductory ASIC flow work spanning RTL synthesis and timing analysis in Synopsys Design Compiler and Synopsys VCS.
Experience
Incoming Implementation Engineer Intern
ARM // San Diego, CA
Planned focus on physical design and implementation for CPU/GPU cores and SoCs, including synthesis, floorplanning, place and route, static timing analysis, verification, and PPAT trade-off analysis.
Hardware Design Intern
Digital Force Technologies (DFT) // San Diego, CA
Implemented instruction fetch, instruction decode, and ALU RTL for a custom RISC-V FPGA processor, then verified behavior through simulation, waveform inspection, and iterative debugging.
Undergraduate Researcher
VSCLab, UC Riverside // Riverside, CADeveloping an open-source RISC-V CPU core and verification infrastructure while building proficiency in constraint-driven synthesis flows and SDC timing constraints in Synopsys Design Compiler.
Projects
Project Obsidian: 2D Graphics Accelerator
Designing a specialized 2D graphics accelerator for a fantasy-console architecture, with work spanning microarchitecture, verification, and physical design. Current implementation includes an APB slave interface, on-chip SRAM, a dedicated 2D blitter engine, and a VGA-compatible video scanner.
Two-Level Cache RTL (L1-L2)
Implemented configurable Verilog RTL for L1 and L2 caches with LRU replacement plus write-back and write-allocate policies. Validated behavior in Synopsys VCS and Verdi using crafted access traces, hit/miss instrumentation, and waveform inspection across multiple cache parameters.
Contact
Open to conversations around RTL design, computer architecture, VLSI implementation, and hardware engineering opportunities.