I work at the boundary of physics and abstraction — RTL design, verification, and the full RTL-to-GDSII flow — with the same instinct: keep the model honest. Currently architecting a 2D graphics accelerator for academic tapeout, refining timing constraints in Synopsys DC, and authoring a two-level cache hierarchy from first principles.
implementation engineer intern · san diego · synthesis · place & route · sta
undergraduate researcher · custom risc-v · sdc constraints · synopsys dc
hardware design intern · san diego · risc-v fpga · ifu/idu/alu rtl
A specialized Blitter that offloads pixel-copy from a custom Fantasy Console host CPU. Memory-mapped APB slave, on-chip SRAM, dedicated compute engine, VGA scanner. Driven through synthesis, place-and-route, and timing closure on the Synopsys toolchain — targeting clean DRC/LVS sign-off and an academic tapeout.
Configurable L1–L2 RTL: parametric sets / ways / line size, LRU replacement, write-back / write-allocate. Tag, data, and valid structures with a simple memory model emulating main-memory latency. Validated in Synopsys VCS against crafted access traces, with hit/miss counters and Verdi waveforms confirming LRU and write policy across configurations.